Engineering_Header.hh

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/*  HiRISE Engineering_Header
 
PIRL CVS ID: Engineering_Header.hh,v 1.28 2020/02/14 01:17:18 schaller Exp
 
Copyright (C) 2004-2020 Arizona Board of Regents on behalf of the Lunar and
Planetary Laboratory at the University of Arizona.
 
Licensed under the Apache License, Version 2.0 (the "License"); you may not use
this file except in compliance with the License. You may obtain a copy of the
License at
 
   http://www.apache.org/licenses/LICENSE-2.0
 
Unless required by applicable law or agreed to in writing, software distributed
under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, either express or implied. See the License for the
specific language governing permissions and limitations under the License.
*/
#ifndef _HiRISE_Engineering_Header_
#define _HiRISE_Engineering_Header_
 
//  UA::HiRISE
#include    "Data_Component.hh"
 
#if defined (INCLUDE_PVL)
//  idaeim::PVL
#include    "PVL.hh"
#endif
 
#include    <iostream>
 
namespace UA
{
namespace HiRISE
{
/*******************************************************************************
    Engineering_Header
*/
class Engineering_Header
:   public Data_Component
{
public:
/*==============================================================================
    Constants:
*/
static const char* const
    ID;
 
static const char* const
    NAME;
 
enum Element
    {
    LUT_Compressed,
    Binning_Factor,
    Delta_Line_Time,
    TDI_Stages,
    Trimming,
    Post_Binned_Lines,
    FPGA_Code_Version,
    DLL_Locked,
    DLL_Reset_Count,
    DLL_Locked_Once,
    DLL_Frequency_Correct_Count,
    ADC_Timing_Settings,
    Pad,
 
    //  The total number of Elements:
    Total_Elements
    };
 
static const char*
    NAMES[];
 
static const Index
    COMPONENT_BYTES;
 
static const Index
    OFFSETS[];
 
static const Index
    ARRAY_COUNTS[][2];
 
static const char* const
    FORMAT_FILENAME;
 
enum DLL_Clock
    {
    FIRST_CLOCK,
    SECOND_CLOCK
    };
 
enum ADC_Timing_Field
    {
    ADC_RESET_TIMING,
    ADC_IMAGE_TIMING
    };
 
static const u_int_32
    ADC_TIMING_MASKS[2];
 
/*==============================================================================
    Constructors
*/
Engineering_Header ();
 
explicit Engineering_Header (std::istream& stream);
 
Engineering_Header (const Engineering_Header& component,
    bool data_duplicate = true);
 
Engineering_Header& operator= (const Engineering_Header& component);
 
/*==============================================================================
    Accessors
*/
std::string id () const;
 
const char* name () const;
 
u_int_32 ADC_timing (Index channel, ADC_Timing_Field field) const;
 
/*==============================================================================
    Printing
*/
std::ostream& print
    (std::ostream& stream = std::cout, bool verbose = false) const;
 
#if defined (INCLUDE_PVL)
/*==============================================================================
    PVL
*/
idaeim::PVL::Aggregate* PVL () const;
 
idaeim::PVL::Aggregate* PVL_description () const;
 
#endif  // defined (INCLUDE_PVL)
 
/*==============================================================================
    Validation
*/
bool is_valid () const;
};
 
}   //  namespace HiRISE
}   //  namespace UA
#endif